KEYNOTE

SAFETY in cars 

Franck Galtié, NXP Toulouse, France

Functional Safety and reliability have always been tightly connected. The Hardware integrity of a safe system is fully dependent on the hardware random faults, which drastically influence the Safety concept based on very old reliability handbooks (SN29500, former IEC61508, FIDES). The upcoming so-called Software Defined Vehicle (SDV) becomes a game changer that does heavily impact the approach of Functional Safety. The balance between hardware and software must be revisited while the hardware safety concept moves to different challenges, mostly related to dependability and availability. Electrification, and in the future autonomous driving, do change the operating lifetime of the system. The extended mission profile does have an impact on the Safety related residual failure rate and therefore on the safety concept. The main challenge is then to define more realistic base failure rate of the semiconductor elements.

INVITED PAPERS

From AI-powered Image Classification to GenAI: Possibilities for Modern Image-based Failure Analysis 

Roland Brunner, Materials Center Leoben Forschung GmbH, Austria

3D integration technologies are essential for classical microelectronics but also for upcoming quantum computing devices. Ongoing miniaturization in this context challenges modern failure analysis and consolidates the need for efficiently detecting defects. Here, we review our latest work in context to AI-powered failure analysis workflows. Non-destructive scanning acoustic microscopy (SAM) is applied to measure the underlying image data. Examples comprise through silicon vias (TSVs), to wafer to wafer bonding technologies or flip chip bonding, etc. . We show how artificial intelligence-based image enhancement, advanced object detection and semantic segmentation drives modern failure analysis. For the segmentation we utilize a ML-based technique, whereas for the object detection, methods like YOLO etc. are utilized.  Furtherer different image enhancement model architectures are tested on their ability to generalize on a large dataset and restrict unphysical hallucination but also in terms of evaluation time and power consumption. Note, that our presented workflow is not limited to SAM generated image data and can be extended to other imaging techniques.

Reliability tests of an atom chip for quantum gravimetry

Marc Wurz, Institut for microproduktionstechnik, University of Hannover, Germany

Measuring gravity requires ever more precise measurement methods. One possibility is the use of quantum gravimetry using Bose-Einstein condensates. Here, a defined number of atoms are electro-magnetically trapped by an atom chip and the gravitational acceleration is measured in an interferometric setup. The structure of the atom chip consists of two parts that have to be reliably joined together. The base material of the two chips is silicon. Gold is used as the conductor material. Since Bose-Einstein condensates can only be produced in an ultra-high vacuum atmosphere, a key requirement is that no polymers are used, as these can outgas. As it is necessary to do without polymers, the electrical conductors are inserted into the chip. Deep reactive ion etching is used for this purpose, followed by passivation using PECVD. As the surface of the chip acts as a mirror in the application, the upper chip must be polished using chemical-mechanical polishing after the electrical conductors have been produced. Another requirement is a high current-carrying capacity of the electrical conductors, which must carry a pulsed current of 2A with a conductor cross-section of 20 * 50 µm². This causes the conductor to heat up, which can result in delamination due to the different thermal expansion coefficients. Furthermore, a low-melting joining process is used here in order to keep the thermal load as low as possible when joining the chips. To ensure reliability, current load tests and mechanical and thermal tests were carried out.

Marc Christopher Wurz has more than 20 years of experience in the field of micro- and nanosystem technology. In 2009, he received his phD degree in microsystem technology from Leibniz University Hannover. Since 2022, he has been head of the Institute for Microproduction Technology, where he operates a clean room with a production line for micro- and nanosystems. He is a member of the board of the “Production Technology Center Hannover” and the “Laboratory of Nano and Quantum Engineering.” His research activities focus on magnetic sensors and actuators, new technologies for system integration in combination with new manufacturing technologies for microsystems technology. Over the past 10 years, he has expanded his research activities to include photonics and quantum systems. These activities are supported by participation in two clusters of excellence (PhoeinxD and Quantum Frontiers). The research work is leading to the development of atomic chips for the generation of Bose-Einstein condensates under space conditions. He has published his results in more than 200 publications. In addition, he has filed more than 30 patent applications.

Wire bonding technology : thermomechanical stresses characterisation and modelling

Merouane OUHAB, Mitsubishi Electric R&D Centre Europe, France

Wire bonding technology is widely used in power electronics to make electrical interconnections. IGBT power modules, in particular, use thick aluminum wires to drive a power current from a source to a load obeying complex mission profiles. During operation, the aluminum wires are subjected to high thermomechanical stresses due to temperature cycles, which leads to failure under long term exposure conditions. In the presentation, a large experience of lifetime testing, characterization and modelling of this failure is highlighted

Characterization Methods for Evaluating Charge Carrier Trapping Mechanisms of SiC Power MOSFETs

Ivana Ferdinand Kovacevic-Badstuebner, ETH Zurich, Switzerland

Before a full device fabrication, test structures such as MOS-capacitors (MOSCAPs) are typically used to evaluate how specific fabrication steps affect the quality of SiC-oxide interface. The conductance method is a well-known characterization method for MOSCAPs, allowing to extract both the amount of traps and their time responses. An application of the conductance method to SiC power MOSFETs was also shown to be a useful method to analyze the SiC-oxide interface that can be further utilized for understanding the interface behavior after reliability tests. The importance of ac- and ramp-C-V MOSCAP/MOSFET characterization is on the other hand two-fold: Measurements of application-relevant C-V characteristics and evaluation of the quality of SiC-oxide interface. However, MOSCAPs do not allow for evaluating the two-voltage dependent behavior of MOSFETs during switching. Understanding the footprint of the slow and fast traps within the measured C-V and I-V device characteristics of SiC power MOSFETs is of great interest for both device manufacturers and system engineers. With an assistance of advanced simulations, evidence of the dynamic nature of traps was observed for SiC power MOSFETs at the switching transients. Overall, the selected examples point out that combining experimental characterization and intricate simulations is the best way to understand the gate-oxide reliability of SiC power MOSFETs relevant for their field operation.